\newpage
\section{Cookbook for PC}



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\subsection{Synthesizing the Bitstream with Embedded Firmware and Key Memory}
\label{generateall}
\textbf{Prerequisites: ICCFPGA-Repository \ref{iccfpgarepo}, RISC-V Toolchain \ref{riscvtoolchain}, Vivado \ref{vivado}}\\

There is a script in the `iccfpga-core`-Repository which conveniently does the following:

\begin{itemize}
 \item Recompile the RISC-V firmware
 \item Resynthesize the Core with embedded firmware and API- and AES-keys
 \item Generate XSVF-files for FPGA and QSPI-flash
\end{itemize}

This is the most non-interactive way of completly rebuilding the core file without even having to open Vivado.\\

\begin{lstlisting}[language=bash]
# export path to the installation directory of vivado
export VIVADOPATH=<vivado-bin-directory>

# export path to the risc-v toolchain
export PATH=$PATH:/opt/rv32im/bin


# start the build process
cd iccfpga/iccfpga-core/utils
./generate_all.sh
\end{lstlisting}

The script will try to compile the RISC-V firmware and completly resynthesize the Core with the firmware embedded.

It also generates XSVF-files which can be replayed on a Raspberry Pi (described in \ref{xsvfpi}).


\textbf{Note: In debugging mode, the firmware can be uploaded via RISC-V OpenOCD debugger. In production mode (locked JTAG) this is the only way
to update the firmware.}



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\subsection{Changing the API or AES key}

\textbf{Prerequisites: ICCFPGA-Repository \ref{iccfpgarepo}, Python}\\

The API and AES keys are, by default, in a file called `data.coe` in the `iccfpga/iccfpga-core/secure-data/` directory.

The file is generated by a python script that reads `keydata.txt` from the same directory. 

It can be executed with:

\begin{lstlisting}[language=bash]
cd iccfpga/iccfpga-core/secure-data
python ./generate_coe.py
\end{lstlisting}

After regenerating the `data.coe` file, the XSVF file has to be completely resynthesized by running the script described in \ref{generateall}.



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\subsection{Connecting Vivado to a Virtual Cable Server, using a Raspberry Pi}
\label{vivadoxvcs}
\textbf{Prerequisites: Starting a Virtual Cable Server \ref{cableserver}, Vivado \ref{vivado}, Jumper J9 (FPGA) on ``PI''}\\

TODO: some pictures 


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\subsection{Connecting Vivado to a Xilink USB JTAG Adapter}
\label{vivadousb}

\textbf{Prerequisites: Clone the ICCFPGA-Repository \ref{iccfpgarepo}, Install Vivado \ref{vivado}, Jumper J9 (FPGA) on ``CON'' \ref{jumpers}}\\

This guide explains how to flash bitstreams to QSPI flash, using a Xilink USB JTAG adapteR.

\begin{center}
 \includegraphics[width=8cm]{img/dlc9g.jpg}
\end{center}

\begin{enumerate}
\item Start the Vivado hardware server
\begin{lstlisting}[language=none,caption={Starting hw\_server}]
pc:~/xilinx/Vivado/2018.2/bin$ sudo ./hw_server

****** Xilinx hw_server v2018.2
  **** Build date : Jun 14 2018-20:18:37
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

INFO: hw_server application started
INFO: Use Ctrl-C to exit hw_server application

INFO: To connect to this hw_server instance use url: TCP:192.168.0.100:3121
\end{lstlisting}
\item Connect the hardware server to the ICCFPGA module by using the hardware manager
\begin{center}
 \includegraphics[width=18cm]{img/hw1.png}
\end{center}







\section{Uploading a Bitstream to the FPGA}

\textbf{Prerequisites: Connect Vivado \ref{vivadoxvcs} or \ref{vivadousb}}\\



\begin{center}
 \includegraphics[width=10cm]{img/hw2.png}
\end{center}
\item Click \textbf{Program Device...} and select your bitstream file
\begin{center}
 \includegraphics[width=10cm]{img/hw3.png}
\end{center}
\end{enumerate}

%\clearpage
\textbf{Note:} This only loads the bitstream onto the ICCFPGA but it is not stored permanently in the QSPI flash. If the bitstream has to be stored permanently on the module, the QSPI flash has to be added (it is already shown in the dialogue before) and has to be programmed.

\begin{center}
 \includegraphics[width=10cm]{img/hw4.png}
\end{center}

\textbf{Note:} This flashing only works if the flag `CFG\_AES\_ONLY` is not enabled in \ref{aesenable}! The reason is how the QSPI flash is connected to the ICCFPGA. The indirect programming mode is used in which the FPGA is configured with a bitstream that gives Vivado access to the QSPI flash. Unfortunately there is no encrypted version of this bitstream. If the flag is enabled, the QSPI flash only can be written through the RISC-V soft CPU, which has access to the flash.
 
 
 
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\section{Flashing Bitstreams to QSPI Flash}
\label{flash}

\textbf{Prerequisites: Connected Vivdo \ref{vivadoxvcs} or \ref{vivadousb}}\\

TODO some pictures




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% \subsection{Creating an SVF File}
% \label{svffile}
% 
% \textbf{Prerequisites: Connected Vivdo \ref{vivadoxvcs} or \ref{vivadousb}}\\
% 
% This guide explains how to manually create an SVF file of a bitstream that you want to upload to the ICCFPGA module's RAM from a Raspberry Pi. 
% 
% To complete this guide, you need to install the Vivado hardware manager. See \ref{vivado}.
% 
% \begin{enumerate}
% \item Start the Vivado hardware server, and click \textbf{Create SVF Target...}
% \begin{center}
%  \includegraphics[width=7cm]{img/svf1.png}
% \end{center}
% \item If you want, enter a name for your file, or just click \textbf{OK}
% \begin{center}
%  \includegraphics[width=9cm]{img/svf2.png}
% \end{center}
% \item On the next screen, click \textbf{+} and add Xilinx part `xc7s50ftgb196-1`
% \begin{center}
%  \includegraphics[width=11cm]{img/svf3.png}
% \end{center}
% \item Right-click the device, click \textbf{Add Program Device Operation...}, and select the bitstream file that you want to upload to the FPGA
% \begin{center}
%  \includegraphics[width=11cm]{img/svf5.png}
% \end{center}
% \item Click \textbf{Export SVF...} to create the SVF file
% \end{enumerate}
% 
% \subsection{Uploading SVF Files to the ICCFPGA Module}
% \label{uploadsvf}
% 
% This guide explains how to upload a bitstream to the ICCFPGA module from an SVF file.
% 
% To complete this guide, you need to an SVF file. See \ref{svffile}.
% 
% If you're using a Raspberry Pi 3, remove the -4s flag.
% 
% \begin{lstlisting}[language=bash]
% $ sudo svftool-gpio -4s svftarget_0.svf
% \end{lstlisting}
% 
% When the file has finished uploading, LED D1 on the ICCFPGA module should flash to confirm that a bitstream was successfully loaded and the system is running.
% 
% Now the bitstream is running on the ICCFPGA module, you can connect to UART and start using the API. See \ref{api}
% 

 
 
 





 
